63 research outputs found
Efficient Design of Triplet Based Spike-Timing Dependent Plasticity
Spike-Timing Dependent Plasticity (STDP) is believed to play an important
role in learning and the formation of computational function in the brain. The
classical model of STDP which considers the timing between pairs of
pre-synaptic and post-synaptic spikes (p-STDP) is incapable of reproducing
synaptic weight changes similar to those seen in biological experiments which
investigate the effect of either higher order spike trains (e.g. triplet and
quadruplet of spikes), or, simultaneous effect of the rate and timing of spike
pairs on synaptic plasticity. In this paper, we firstly investigate synaptic
weight changes using a p-STDP circuit and show how it fails to reproduce the
mentioned complex biological experiments. We then present a new STDP VLSI
circuit which acts based on the timing among triplets of spikes (t-STDP) that
is able to reproduce all the mentioned experimental results. We believe that
our new STDP VLSI circuit improves upon previous circuits, whose learning
capacity exceeds current designs due to its capability of mimicking the
outcomes of biological experiments more closely; thus plays a significant role
in future VLSI implementation of neuromorphic systems
Design and Implementation of BCM Rule Based on Spike-Timing Dependent Plasticity
The Bienenstock-Cooper-Munro (BCM) and Spike Timing-Dependent Plasticity
(STDP) rules are two experimentally verified form of synaptic plasticity where
the alteration of synaptic weight depends upon the rate and the timing of pre-
and post-synaptic firing of action potentials, respectively. Previous studies
have reported that under specific conditions, i.e. when a random train of
Poissonian distributed spikes are used as inputs, and weight changes occur
according to STDP, it has been shown that the BCM rule is an emergent property.
Here, the applied STDP rule can be either classical pair-based STDP rule, or
the more powerful triplet-based STDP rule. In this paper, we demonstrate the
use of two distinct VLSI circuit implementations of STDP to examine whether BCM
learning is an emergent property of STDP. These circuits are stimulated with
random Poissonian spike trains. The first circuit implements the classical
pair-based STDP, while the second circuit realizes a previously described
triplet-based STDP rule. These two circuits are simulated using 0.35 um CMOS
standard model in HSpice simulator. Simulation results demonstrate that the
proposed triplet-based STDP circuit significantly produces the threshold-based
behaviour of the BCM. Also, the results testify to similar behaviour for the
VLSI circuit for pair-based STDP in generating the BCM
Design techniques for low power mixed analog-digital circuits with application to smart wireless systems.
This dissertation presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology. The application domain of the devised techniques is radio frequency identification (RFID) systems, however the presented techniques are applicable to wide range of mixed mode analog-digital applications. Hence the techniques herein apply to a range of smart wireless or mobile systems. The integration of both analog and digital circuits on a single substrate has many benefits such as reducing the system power, increasing the system reliability, reducing the system size and providing high inter-system communications speed - hence, a cost effective system implementation with increased performance. On the other hand, some difficulties arise from the fact that standard low-cost CMOS technologies are tuned toward maximising digital circuit performance and increasing transistor density per unit area. Usually these technologies have a wide spread in transistor parameters that require new design techniques that provide circuit characteristics based on relative transistor parameters rather than on the absolute value of these parameters. This research has identified new design techniques for mostly analog and some digital circuits for implementation in standard CMOS technologies with design parameters dependent on the relative values of process parameters, resulting in technology independent circuit design techniques. The techniques presented and discussed in this dissertation are (i) applied to the design of low-voltage and low-power controlled gain amplifiers, (ii) digital trimming techniques for operational amplifiers, (iii) low-power and low-voltage Schmitt trigger circuits, (iv) very low frequency to medium frequency low power oscillators, (v) low power Gray code counters, (vi) analog circuits utilising the neuron MOS transistor, (vii) high value floating resistors, and (viii) low power application specific integrated circuits (ASICs) that are particularly needed in radio frequency identification systems. The new techniques are analysed, simulated and verified experimentally via five chips fabricated through the MOSIS service.Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 200
Physical implementation of pair-based spike-timing-dependent plasticity
Objective Spike-timing-dependent plasticity (STDP) is one of several plasticity rules which leads to learning and memory in the brain. STDP induces synapticweight changes based on the timing of the pre- and postsynaptic neurons. A neural network which can mimic the adaptive capability of biological brains in the temporal domain, requires the weight of single connections to be altered by spike timing. To physically realise this network into silicon, a large number of interconnected STDP circuits on the same substrate is required. This imposes two significant limitations in terms of power and area. To cover these limitations, very large scale integrated circuit (VLSI) technology provides attractive features in terms of low power and small area requirements. An example is demonstrated by (Indiveri et al. 2006). The objective of this paper is to present a newimplementation of the STDPcircuit which demonstrates better power and area in comparison to previous implementations.
Methods The proposed circuit uses complementary metal oxide semiconductor (CMOS) technology as depicted in Fig. 1. The synaptic weight can be stored on a capacitor and charging/discharging current can lead to potentiation and depression.
Results and Conclusion: HSpice simulation results demonstrate that the average power, peak power, and area of the proposed circuit have been reduced by 6, 8 and 15%, respectively, in comparison with Indiveri's implementation. These improvements naturally lead to packing more STDP circuits onto the same substrate, when compared to previous proposals. Hence, this new implementation is quite interesting for real-world large neural networks
Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing
We present new computational building blocks based on memristive devices.
These blocks, can be used to implement either supervised or unsupervised
learning modules. This is achieved using a crosspoint architecture which is an
efficient array implementation for nanoscale two-terminal memristive devices.
Based on these blocks and an experimentally verified SPICE macromodel for the
memristor, we demonstrate that firstly, the Spike-Timing-Dependent Plasticity
(STDP) can be implemented by a single memristor device and secondly, a
memristor-based competitive Hebbian learning through STDP using a synaptic network. This is achieved by adjusting the memristor's
conductance values (weights) as a function of the timing difference between
presynaptic and postsynaptic spikes. These implementations have a number of
shortcomings due to the memristor's characteristics such as memory decay,
highly nonlinear switching behaviour as a function of applied voltage/current,
and functional uniformity. These shortcomings can be addressed by utilising a
mixed gates that can be used in conjunction with the analogue behaviour for
biomimetic computation. The digital implementations in this paper use in-situ
computational capability of the memristor.Comment: 18 pages, 7 figures, 2 table
An Analytical Approach for Memristive Nanoarchitectures
As conventional memory technologies are challenged by their technological
physical limits, emerging technologies driven by novel materials are becoming
an attractive option for future memory architectures. Among these technologies,
Resistive Memories (ReRAM) created new possibilities because of their
nano-features and unique - characteristics. One particular problem that
limits the maximum array size is interference from neighboring cells due to
sneak-path currents. A possible device level solution to address this issue is
to implement a memory array using complementary resistive switches (CRS).
Although the storage mechanism for a CRS is fundamentally different from what
has been reported for memristors (low and high resistances), a CRS is simply
formed by two series bipolar memristors with opposing polarities. In this paper
our intention is to introduce modeling principles that have been previously
verified through measurements and extend the simulation principles based on
memristors to CRS devices and hence provide an analytical approach to the
design of a CRS array. The presented approach creates the necessary design
methodology platform that will assist designers in implementation of CRS
devices in future systems.Comment: 12 pages, 10 figures, 4 table
Secure Goods Supply Chain and Key Exchange with Virtual Proof of Reality
A new security protocol of {\it virtual proof of reality} (VP) is recently proposed by Ruhrmair {\it et al.} The VP allows one party, the prover, making a physical statement to the other party, the verifier, over a digital communication channel without using any secret keys except the message sent between these two parties. The physical statement could be a physical feature---eg. temperature---or phenomena---eg. destruction---of the hardware in the prover\u27s system. We present two applications---secure key exchange and secure goods supply chain---building on the VP of temperature, location, and destruction. Moreover, we experimentally demonstrate the first electrical circuit-based VP of destruction through the proposed hardware security primitive---a hybrid memristor and physical unclonable function (memristor-PUF) architecture, which takes advantage of the PUF extracted from static variations of CMOS devices inherent to the fabrication process and dynamic variations attributed to switching variabilities of nano memristors
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